The present invention relates to a DRAM device and an LSI comprising the DRAM device and an LSI with a logic function in a mixed manner fabricated on the same chip.
Conventionally, two wordline driving methods for a DRAM device have been employed, which are:
(1) Two stage decode method using NMOS PA1 (2) Vpp method using PMOS PA1 plural cell arrays two-dimensionally arranged in column and row directions; PA1 a wordline driving section having a drive transistor in each row for transferring a charge to a corresponding cell in the plural cell arrays by raising a voltage on a wordline selected by a plural stage decode method; PA1 a first generating section for generating a drive signal for driving a wordline which is supplied to the drive transistor, the drive signal being generated based on a stored charge in a capacitor; and PA1 a second generating section for generating a control signal for controlling the gate of the drive transistor in a chip of the DRAM device by a charge pump circuit. PA1 plural cell arrays two-dimensionally arranged in column and row directions; PA1 a wordline driving section having a drive transistor in each row for transferring a charge to a corresponding cell in the plural cell arrays by raising a voltage on a wordline selected by a plural stage decode method; PA1 a bitline equalization signal driving section in which a bitline equalization signal is equalized by raising a voltage; PA1 a first generating section for generating the bitline equalization signal based on a stored charge in a capacitor; and PA1 a second generating section for generating a control signal for controlling the gate of the drive transistor in a chip of the DRAM device by a charge pump circuit. PA1 plural cell arrays two-dimensionally arranged in column and row directions; PA1 a wordline driving section having a drive transistor in each row for transferring a charge to a corresponding cell in the plural cell arrays by raising a voltage on a wordline selected by a plural stage decode method; PA1 a bitline separation signal driving section for transferring a charge between a bitline and a sense amplifier by raising a voltage of a bitline separation signal; PA1 a first generating section for generating a bitline separation signal based on a stored charge in a capacitor; and PA1 a second generating section for generating a control signal for controlling the gate of the drive transistor in a chip of the DRAM device by a charge pump circuit. PA1 plural cell arrays two-dimensionally arranged in column and row directions; PA1 a wordline driving section having a drive transistor in each row for transferring a charge to a corresponding cell in the plural cell arrays by raising a voltage on a wordline selected by a plural stage decode method; PA1 a bitline equalization signal driving section for effecting equalization by raising a voltage of a bitline equalization signal; PA1 a bitline separation signal driving section for transferring a charge between a bitline and a sense amplifier by raising a voltage of a bitline separation signal; PA1 a first generating section for generating a drive signal for driving a wordline which is supplied to the drive transistor, the drive signal being generated based on a stored charge in a capacitor; PA1 a second generating section for generating the bitline equalization signal based on a stored charge in a capacitor; PA1 a third generating section for generating the bitline separation signal based on a stored charge in a capacitor; and PA1 a fourth generating section for generating a control signal for controlling the gate of the drive transistor in a chip of the DRAM device by a charge pump circuit.
First of all, (1) two stage decode method will be described. The two stage decode method is performed in the following manner. That is, in FIG. 24, one row decoder 1i (i=0-63) is selected based on a combination of a precharge signal PRCHn and an address signal XA0-XA7, XB0-XB7. Then, when one WDRVnj driver 3j (j=0-3) is selected based on a combination of a precharge signal PRCHn and an address signal A0R, A1R, one wordline driver (WL driver) 2i-j (i=0-63, J=0-3) is selected in correspondence to the WDRVnj signal to finally drive one wordline WL. In FIG. 1, though a decoder corresponding to the WDRVnj driver 3j is not shown, the decoder corresponding to the WDRVnj driver 3j is actually provided.
FIG. 25 shows a constitution comprising a row decoder 10 corresponding to a row decoder 1i shown in FIG. 24 and a WL driver 20-m (m=0-3) corresponding to a WL driver 2i-j (for example, i=0, j=0-3) shown in FIG. 24. WL drivers 20-m are respectively connected to a wordline WLm.
In FIG. 25, a PMOS transistor P1, to whose gate a precharge signal PRCHn is input, and whose source is connected to a power supply Vcc, an NMOS transistor N1, to whose gate an address signal XAi is input, and an NMOS transistor N2, to whose gate an address signal XBj is input, and whose source is connected to the ground, are in series connected and inserted between the power supply Vcc and the ground. A connection point between the drain of the PMOS transistor P1 and the drain of the NMOS transistor N1 is connected with the drain of a PMOS transistor P2, whose source is connected to the power supply Vcc, the common gate between a PMOS transistor P3 and an NMOS transistor N3 in series connected with each other, the common gate between a PMOS transistor P4 and an NMOS transistor N4 connected in series with each other and the gate of an NMOS transistor N7 whose source is grounded.
The source of the PMOS transistor P2 is connected to the power supply Vcc and the gate thereof is connected to the common drain between the PMOS transistor P3 and the NMOS transistor N3 connected in series with each other. The sources of the NMOS transistors N3, N4 are grounded. The common drain between the PMOS transistor P4 and the NMOS transistor N4 is connected to the drain of the NMOS transistor N5. The gate of NMOS transistor N5 is connected to the power supply Vcc, and the source of the NMOS transistor N5 is connected to the gate of the NMOS transistor N6.
The NMOS transistor N6 and the NMOS transistor N7 are connected in series with each other. A WDRVn0 signal is input to the drain of the NMOS transistor N6 and the source of the NMOS transistor N7 is grounded. A wordline drive signal WL0 is obtained from a connection point between the source of the NMOS transistor N6 and the drain of the NMOS transistor N7.
In the above mentioned constitution, the PMOS transistors P1-P4, the NMOS transistors N1-N4 constitute a row decoder 10 and the NMOS transistors N5, N6, N7 constitute a WL driver 20-0.
Besides, the constitution further comprises: WL drivers 20-1, 20-2, 20-3, each of which has the same constitution as the WL driver 20-0, which is connected to the common drain between the PMOS transistor P4 and the NMOS transistor N4 and the common drain between the PMOS transistor P1 and the NMOS transistor N1, wherein a WDRVn1 signal, a WDRBn2 and a WDRVn3 signal are respectively input to the WL drivers 20-1, 20-2, 20-3.
FIG. 26 is a circuit diagram in which a WDRVnj driver shown in FIG. 24 is constructed with NMOS. Since this constitution is almost the same as the constitution shown in FIG. 25 in which the row decoder 10 and the WL driver 20-0 are combined, wherein address inputs XAj, XBj are only replaced with A0R, A0R bar A1R, A1R bar, detailed description is omitted.
An operational principle and operational limit of the above mentioned constitution will be described. Selection of a wordline is performed in two stages, one of which is a circuit shown in FIG. 26 in which a WDRVnj signal is generated from a WDRV signal and the other of which is a circuit shown in FIG. 25 in which one WL driver is selected by the WDRVnj signal and a wordline is finally selected.
In FIG. 25, when a precharge signal PRCHn is high and one row decoder (in this case row decoder 10) is selected by a predecoded address signal XAi and predecoded signals XB0-XB3, the drain of the NMOS transistor N5 is Vcc and a node A is charged to Vcc-Vth. Here, Vth is a threshold value of the NMOS transistor N5. This value is, by a back gate bias effect, increased higher than a value (at the lowest, on the order of 0.5V) when an ordinary source is GND and considered to be on the order of 1.5V, since the source is raised to Vcc-Vth. Thereafter, when Vcc=5V, the WDRVnj signal which is decoded at A0R, A1R of FIG. 26 and then is input to the drain of the NMOS transistor N6 for wordline driving of FIG. 25 is raised for 0 to 7.5V. In that case, the node A is raised from Vcc-Vth to as high as about 10V by a parasitic capacitance C1 between the drain and gate of the NMOS transistor N6 and WL0 is raised from 0 to 7.5V while Vth of the NMOS transistor N6 is held as it is. A circuit which generates a WDRVnj of FIG. 26 operates in absolutely the same principle.
While the above mentioned circuit almost normally operates at a high speed in a Vcc=5V system, there arises a case where an increasing speed of a wordline is lowered and thereby the wordline cannot be driven when Vcc is reduced to Vcc=3.3V. The reason why is that a charge voltage Vcc-Vth of the node A becomes smaller and thereby the node A is not sufficiently booted when a WDRVAnj signal is input. For example, when Vcc=3V as the worst condition (guarantee of operation is required at 3.3V.+-.10%), if Vth=1.5V in light of a back gate bias effect (Vth cannot be so much reduced in the case where increase in a standby current by a subthreshold current is considered even if Vcc is lowered), only Vcc=1.5V is allowed, the node A is raised from 1.5V to only about 4.5V, thereby a wordline cannot be raised to a desired 4.5V but only to 4.5-(Vth of the NMOS transistor N6)=4.5-1.5=3.0V and as a result the wordline cannot be driven in a normal state. In such a condition, an increasing speed of a wordline is also slowed by a great margin. As described above, it is understood that a wordline driving circuit of NMOS is a circuit which cannot be used in DRAM at a Vcc equal to or lower than 3.3V.
Then, (2) Vpp method using PMOS will be described, in which the problem encountered with the two stage method is overcome.
In FIG. 27, a PMOS transistor P5 to whose gate a precharge signal PRCHn is input, an NMOS transistor N11 to whose gate an address signal XAi is input and an NMOS transistor N12 to whose gate an address signal XBj is input are connected in series to one another and inserted between a power supply Vcc and the ground. The common drain between the PMOS transistor P5 and the NMOS transistor N11 is connected to the drain of a PMOS transistor P6 whose source is connected to the power supply Vpp, the common gate between a PMOS transistor P7 and an NMOS transistor N13, which are connected in series to each other, and the common gate between a PMOS transistor P8 and an NMOS transistor N14, which are connected in series to each other. The source of the PMOS transistor P7 is connected to the power supply Vpp and the source of the NMOS transistor N13 is grounded. The gate of the PMOS transistor P6 is connected to the common drain between the PMOS transistor P7 and the NMOS transistor N13.
WDRVn0 signal is input to the source of the PMOS transistor P8 and the source of the NMOS transistor N14 is grounded. The common drain between the PMOS transistor P8 and the NMOS transistor N14 is connected to the drain of an NMOS transistor N15, whose source is grounded, and to whose gate a WDRVn0 bar signal is input. A wordline drive signal WL0 is obtained from the common drain between the PMOS transistor P8 and the NMOS transistor N14.
The above mentioned the PMOS transistors P5, P6, P7 and NMOS transistors N11, N12, N13 constitute a row decoder 30 and the PMOS transistor P8 and the NMOS transistors N14, N15 constitute a WL driver 40-0.
The common drain between the PMOS transistor P5 and the NMOS transistor N11 is connected to: a WL driver 40-1, which has the same constitution as the WL driver 40-0, and which outputs a wordline drive signal WL1 by being input with WDRVn1 and a WDRVn1 bar signal; a WL driver 40-2, which outputs a word line drive signal WL2 by being input with WDRVn2 and a WDRVn2 bar signal; and a WL driver 40-3, which outputs a wordline driving signal WL3 by being input with WDRVn3 and a WDRVn3 bar signal.
FIG. 28 is a circuit diagram of the WDRVnj driver 3j constructed with PMOS. Since this constitution is almost the same as the constitution shown in FIG. 27 in which the row decoder 30 and the WL driver 40-0 are combined and constructed in such a manner that not only are the inputs XAi, XBj to the NMOS transistor N11, N12 of the row decoder 30 replaced with A0R (A0R bar) A1R (A1R bar) but also the NMOS transistor N15 is removed, description on the constitution is omitted here.
A method in which the power supply Vpp mentioned above is generated will be described. FIG. 29 is a circuit diagram showing a constitution of a charge pump circuit as a second generating means for generating the power supply Vpp.
In FIG. 29, a node B is connected to a node E through a capacitor C2, the node E is in turn connected to the drains of respective NMOS transistors N60, N61, N62, and the gate of an NMOS transistor N63. The gate of the NMOS transistor N60 is connected to an output node O and the source thereof is connected to a node G. The node G is connected to a node A through a capacitor C4 and the gate of the NMOS transistor N61. The source of the NMOS transistor N61 is connected to the output node 0.
A node C is connected to a node F through a capacitor C3 and the node F is connected to the gate of the NMOS transistor N62, the source of the NMOS transistor N63 and the drains of the NMOS transistors N64, N65. The source of the NMOS transistor N62 and the drain of the NMOS transistor N63 are connected to the power supply Vcc. The gate of the NMOS transistor N65 is connected to the output node 0, the source thereof is connected to a node H, and the node H is in turn connected to the gate of the NMOS transistor N64 and a node D through a capacitor C5. The source of the NMOS transistor N64 is connected to the output node 0.
Moreover, the node B is connected to the NMOS transistors N60, N61, N62 and the node C is connected to the NMOS transistors N63, N64, N65.
An operational principle of the above mentioned charge pump circuit will be described in reference to a timing chart of FIG. 30.
A, B, C, D of FIG. 30 are input waveforms at the respective nodes A, B, C, D. With these inputs, E, F, G, H which are internal nodes in a circuit shown in FIG. 29, have functions to finally increase Vpp little by little while operating as shown in FIG. 30.
The timing chart is divided into two parts for facilitating a reader's understanding. The upper part is operations of the upper half of the circuit and the lower part is operations of the lower half thereof. Moreover, in order to further facilitate an understanding, the same Vpps are indicated in the respective parts. While the axes of A, B, C, D for the waveform are actually different from those of E, F, G, H and Vpp, the voltage axis (the axis of ordinate) in the latter cases is extended by a factor of 5 as compared to the former cases.
While only the operations of the upper part will be described here, those of the lower part are understood in a similar way.
When an input B is raised from GND to Vcc at a timing, the node E is biased from Vcc to a voltage which is determined by a coupling ratio thereof. In company with this, the node G is raised to Vpp-Vth (Vth is a Vth of the NMOS transistor N61), since a charge is supplied through the NMOS transistor N60. The node G is booted to be raised to a level (the highest potential) which is determined by the coupling ratio from the first Vpp-Vth when an input A is raised to Vcc from GND at a next timing. Thereby, all the charge in the node E is transferred to Vpp through the NMOS transistor N61. That is, the node E and Vpp are equalized. At this time, a voltage level of Vpp is raised.
When the input A is lowered from Vcc to GND in advance, a level of the node G is reduced due to coupling to cut off the NMOS transistor N61. Thereafter, when the input B is lowered in a similar way from Vcc to GND, not only is the node E reduced to a lower level due to coupling, but the node G is also reduced to the same level through the NMOS transistor N60. Therefore, the NMOS transistor N61 is perfectly cut off. Since the input C is thereafter raised, the node F of a pump in the lower side is raised and a charge flows into the node E from Vcc through the NMOS transistor N62.
If the above mentioned operations are repeated, a charge flowing in from Vcc is stored in the capacitors C2,C3 and discharged to Vpp in a next cycle.
If not only the pumps in the upper and lower sides are operated in a compensatory manner to increase an operational speed as a whole, but a voltage of the nodes F/E is also received from the counterpart, a path between Vcc and the node E/F can effectively assume an on or off state.
In the drive method, a DC potential, for example Vpp=4.3V, is generated in the chip in the case of Vcc=3.3V using a charge pump circuit shown in FIG. 29 and a wordline is, by use of this, driven in a condition where Vth is not reduced by PMOS and the circuits of FIGS. 27 and 28 are operable even at a lower Vcc than 3.3V.
The charge pump circuit shown in FIG. 29, as described above, is a circuit which generates Vpp=4.3V from Vcc=3.3V and it has two problems. One is that a current of consumption is large in its own circuit. A current equal to a load current theoretically flows in the pump circuit even when a pump efficiency is 100%, that is there is no loss. The reason why is that the capacitors C2, C3 are required to be charged with the same amount of a charge as that which is pumped up. However, as a matter of fact, there is no chance of 100% efficiency but normally at the current state the efficiency is on the order of 50%. The reason of no chance of 100% efficiency is that there is a requirement for a ring oscillator for periodical charge of the nodes A and B, which needs a current of consumption, and quite a large amount of parasitic capacitance is present with a current path in the pump, so that an excessive charge is required for the unnecessary capacitance.
There is a chance where sufficient charge is not stored when the pump is operated at a high speed for production of a current. Besides, there is another chance where a potential of a node is not raised to a sufficient value due to a parasitic resistance. Furthermore, there is still another chance of a leakage of a stored charge due to a subtle mismatch in a timing. Therefore, with superposition of the above mentioned factors, an efficiency of the pump is lowered to the order of 50%. In this case, a current consumed in the pump is twice as large as a Vpp load current and therefore an operational current of DRAM is a large current due to its original magnitude. If a device with a power supply voltage Vcc in the range of 2.5 to 1.8V hereafter appears, there arises a problem that a pump circuit cannot be operable. That is, since if the gate potentials of B, C which are NMOS transistors generating Vpp at a final stage, are not sufficiently boosted, a charge is not transferred. If Vcc is lowered, insufficient transferring results due to poor boosting.